# Zynthian dac adac light ready for codec development

**URL:** <https://discourse.zynthian.org/t/zynthian-dac-adac-light-ready-for-codec-development/10527>\
**Category:** Hardware\
**Created:** [November 18, 2024, 5:48pm UTC](https://discourse.zynthian.org/t/zynthian-dac-adac-light-ready-for-codec-development/10527 "2024-11-18T17:48:19Z")\
**Posts on this page:** 20\
**Page:** 3

<div class="post-metadata">

**Author:** ![riban](https://discourse.zynthian.org/user_avatar/discourse.zynthian.org/riban/32/2331_2.png) [@riban](https://discourse.zynthian.org/u/riban)\
**Post date:** [November 24, 2024, 11:48am UTC](https://discourse.zynthian.org/t/zynthian-dac-adac-light-ready-for-codec-development/10527/41 "2024-11-24T11:48:34Z")

</div>

Cool! I have replaced PCM5102 with spdif-dit and it gives all 8 outputs! I am now working on adding input…

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<div class="post-metadata">

**Author:** ![le51](https://discourse.zynthian.org/user_avatar/discourse.zynthian.org/le51/32/1706_2.png) [@le51](https://discourse.zynthian.org/u/le51)\
**Post date:** [November 24, 2024, 1:12pm UTC](https://discourse.zynthian.org/t/zynthian-dac-adac-light-ready-for-codec-development/10527/42 "2024-11-24T13:12:23Z")

</div>

these overlays are quiet old, so must be adapted using the new clock\_producer or clock\_consumer definition:

> <https://github.com/AkiyukiOkayasu/RaspberryPi_I2S_Master/blob/master/i2smaster.dts>

> <https://github.com/AkiyukiOkayasu/RaspberryPi_I2S_Slave/blob/master/genericstereoaudiocodec.dts>

---

<div class="post-metadata">

**Author:** ![le51](https://discourse.zynthian.org/user_avatar/discourse.zynthian.org/le51/32/1706_2.png) [@le51](https://discourse.zynthian.org/u/le51)\
**Post date:** [November 24, 2024, 1:13pm UTC](https://discourse.zynthian.org/t/zynthian-dac-adac-light-ready-for-codec-development/10527/43 "2024-11-24T13:13:35Z")

</div>

> [@riban](#):
>
> I have replaced PCM5102 with spdif-dit and it gives all 8 outputs!

excellent 👍

---

<div class="post-metadata">

**Author:** ![riban](https://discourse.zynthian.org/user_avatar/discourse.zynthian.org/riban/32/2331_2.png) [@riban](https://discourse.zynthian.org/u/riban)\
**Post date:** [November 24, 2024, 7:13pm UTC](https://discourse.zynthian.org/t/zynthian-dac-adac-light-ready-for-codec-development/10527/44 "2024-11-24T19:13:13Z")

</div>

[test6.dts](https://discourse.zynthian.org/uploads/short-url/4eD4ixuSOmC9dKLRA46sZxyqpjC.dts) (2.2 KB)

Here is the dts with 8 channels of audio output working. If you reverse the order of the `dai-link` sections then you get 8 channels of input. I have not yet figured out how to make both work at the same time. Please feel free to offer assistance…

---

<div class="post-metadata">

**Author:** ![le51](https://discourse.zynthian.org/user_avatar/discourse.zynthian.org/le51/32/1706_2.png) [@le51](https://discourse.zynthian.org/u/le51)\
**Post date:** [November 24, 2024, 10:07pm UTC](https://discourse.zynthian.org/t/zynthian-dac-adac-light-ready-for-codec-development/10527/45 "2024-11-24T22:07:02Z")

</div>

Lots of good news.

Hifiberry Dacx8 set the Pi as master, and I think it should simplify the setup with bitclock-master and frame-master wich looks a bit confusing to me. As is, they differs for the ins and the outs and it seems more logical to have only one bitclock and one frame for the codec (?)

```auto
	fragment@3 {
		// Configure and enable soundcard driver
		target = <&sound>;
		__overlay__ {
			compatible = "simple-audio-card";
			simple-audio-card,name = "zyndacadc-lite";
			status = "okay";
			simple-audio-card,dai-link@0 {
				format = "i2s";
				bitclock-master = <&in_codec>;
				frame-master = <&in_codec>;
				cpu {
					sound-dai = <&i2s_clk_consumer>;
					dai-tdm-slot-num = <2>;
					dai-tdm-slot-width = <32>;
				};
				in_codec: codec {
					sound-dai = <&codec_in>;
				};
			};
			simple-audio-card,dai-link@1 {
				format = "i2s";
				bitclock-master = <&out_codec>;
				frame-master = <&out_codec>;
				cpu {
					sound-dai = <&i2s_clk_consumer>;
					dai-tdm-slot-num = <2>;
					dai-tdm-slot-width = <32>;
				};
				out_codec: codec {
					sound-dai = <&codec_out>;
				};
			};
		};
	};

```

As slaves, pcm5102 and 1808 should do their job once BCK an LRCK are provided without any further configuration I believe.

So rather something like this:

```auto
// Definitions for zynthian DAC ADC lite
/dts-v1/;
/plugin/;

/ {
	compatible = "brcm,bcm2712";

        fragment@0 {
		// Configuration that can set the GPIO pins to enable i2s0 with 4 I2S ports
                target = <&gpio>; // This node will modify the gpio node of the device tree
                __overlay__ { // We are overlaying this config to the exiting device tree
                        rp1_i2s0_8x: rp1_i2s0_8x { // 
                                function = "i2s0"; // Defines the function to enable for these gpio pins
                                pins = "gpio18", "gpio19", "gpio20", "gpio21", "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27"; // Defines the pins to configure
                                bias-disable; // Disable pin bias - Is this volts on the pins?
                                status = "okay"; // Enable this node
                        };
                };
        };

	fragment@1 {
		// Configure the GPIO pins for clock producer
		target = <&i2s_clk_producer>;
		__overlay__ {
			pinctrl-names = "default";			
			pinctrl-0 = <&rp1_i2s0_8x>; // Configure i2s0 to use gpio defined in our fragment@0
			status = "okay";
		};
	};

	fragment@2 {
		// Enable PCM CODEC
		target-path = "/";
		__overlay__ {
			codec_out: codec_out {
				compatible = "linux,spdif-dit";
				#sound-dai-cells = <0>;
				status = "okay";
			};
			codec_in: codec_in {
				compatible = "linux,spdif-dir";
				#sound-dai-cells = <0>;
				status = "okay";
			};
		};
	};

	fragment@3 {
		// Configure and enable soundcard driver
		target = <&sound>;
		__overlay__ {
			compatible = "simple-audio-card";
			simple-audio-card,name = "zyndacadc-lite";
			status = "okay";
			simple-audio-card,dai-link@0 {
				format = "i2s";
				cpu {
					sound-dai = <&i2s_clk_producer>;
					dai-tdm-slot-num = <2>;
					dai-tdm-slot-width = <32>;
				};
				in_codec: codec {
					sound-dai = <&codec_in>;
				};
			};
			simple-audio-card,dai-link@1 {
				format = "i2s";
				cpu {
					sound-dai = <&i2s_clk_producer>;
					dai-tdm-slot-num = <2>;
					dai-tdm-slot-width = <32>;
				};
				out_codec: codec {
					sound-dai = <&codec_out>;
				};
			};
		};
	};
};

```

---

<div class="post-metadata">

**Author:** ![riban](https://discourse.zynthian.org/user_avatar/discourse.zynthian.org/riban/32/2331_2.png) [@riban](https://discourse.zynthian.org/u/riban)\
**Post date:** [November 24, 2024, 10:09pm UTC](https://discourse.zynthian.org/t/zynthian-dac-adac-light-ready-for-codec-development/10527/46 "2024-11-24T22:09:23Z")

</div>

The 1808 needs a MCLK, which RPi does not provide.

---

<div class="post-metadata">

**Author:** ![le51](https://discourse.zynthian.org/user_avatar/discourse.zynthian.org/le51/32/1706_2.png) [@le51](https://discourse.zynthian.org/u/le51)\
**Post date:** [November 24, 2024, 10:14pm UTC](https://discourse.zynthian.org/t/zynthian-dac-adac-light-ready-for-codec-development/10527/47 "2024-11-24T22:14:07Z")

</div>

Do you mean SCKI on pin 6 ? That’s the crystal, and is only needed for ipcm1808 internal operations (as I understand)

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<div class="post-metadata">

**Author:** ![le51](https://discourse.zynthian.org/user_avatar/discourse.zynthian.org/le51/32/1706_2.png) [@le51](https://discourse.zynthian.org/u/le51)\
**Post date:** [November 24, 2024, 10:19pm UTC](https://discourse.zynthian.org/t/zynthian-dac-adac-light-ready-for-codec-development/10527/48 "2024-11-24T22:19:37Z")

</div>

_The PCM1808 device does not require a specific phase relationship between LRCK and SCKI, but does require the synchronization of LRCK and SCKI._

How do you interpret this statement ?

---

<div class="post-metadata">

**Author:** ![riban](https://discourse.zynthian.org/user_avatar/discourse.zynthian.org/riban/32/2331_2.png) [@riban](https://discourse.zynthian.org/u/riban)\
**Post date:** [November 24, 2024, 10:30pm UTC](https://discourse.zynthian.org/t/zynthian-dac-adac-light-ready-for-codec-development/10527/49 "2024-11-24T22:30:14Z")

</div>

It means that SCKI must be an exact multiple of LRCK, i.e. syncronised. The timing between the clock edges (phase) is not important. This means that you cannot have SCKI generated by the crystal and BCK/LRCK generated by the RPi5. All clocks must be generated from the same source. It _may_ be possible to use the `mclk-fs` parameter to set the RPi5 MCLK to an appropriate rate for the PCM1808 then use the 1808 to generate BCLK for the PCM5102.

---

<div class="post-metadata">

**Author:** ![le51](https://discourse.zynthian.org/user_avatar/discourse.zynthian.org/le51/32/1706_2.png) [@le51](https://discourse.zynthian.org/u/le51)\
**Post date:** [November 24, 2024, 11:03pm UTC](https://discourse.zynthian.org/t/zynthian-dac-adac-light-ready-for-codec-development/10527/50 "2024-11-24T23:03:39Z")

</div>

for the Hifiberry dacplusadc that’s how they work:

> <https://github.com/raspberrypi/linux/blob/rpi-6.6.y/arch/arm/boot/dts/overlays/hifiberry-dacplusadc-overlay.dts>

maybe this is specific to pcm1808

---

<div class="post-metadata">

**Author:** ![stojos](https://discourse.zynthian.org/user_avatar/discourse.zynthian.org/stojos/32/10833_2.png) [@stojos](https://discourse.zynthian.org/u/stojos)\
**Post date:** [November 24, 2024, 11:03pm UTC](https://discourse.zynthian.org/t/zynthian-dac-adac-light-ready-for-codec-development/10527/51 "2024-11-24T23:03:50Z")

</div>

@le51 in i2s protocol, master is the one that produces BCK and LRCK (i2s producer). All other parties are slaves (i2s consumers) and use BCK and LRCK to transmit their data on their dedicated data lines. LRCK clock (left/right clock) determine when to start sending bits for left or right channel. BCK tells when to send bits. BCK is 64 \* LRCK. LRCK and BCK lines are shared by all parties in i2s protocol, dac, adc and SoC.

To be able to produce or listen BCK and LRCK all parties must have their internal clock - what I would call master clock. This is typically a oscillator that divided its frequencies by some number to get in sync with BCK and LRCK frequencies. Some dac and adac microchip have internal oscillator and they can get them in sync with BCK and LRCK, while some don’t. 1808 don’t so additional oscillator is there to supply the master clock. Master clock, BCK and LRCK must be in sync for 1808 to work. 5102 is also set to use external master clock instead of using internal. I have supplied master clock to rpi to use it but rpi i2s protocol implementation probably does not need it and use its internal clock to sync with BCK and LRCK.

I have decided to set 1808 to be master and produce BCK and LRCK based on master clock because it can be done simple by configuration of two pins MD0 and MD1. Otherwise, rpi will need to listen on master clock and make BCK and LRCK to sync to it in addition to its internal clock. This later option is more complicated to do and would required more i2s coding and pin 7 to be listened by rpi2 i2s protocol for producing BCK and LRCK.

---

<div class="post-metadata">

**Author:** ![riban](https://discourse.zynthian.org/user_avatar/discourse.zynthian.org/riban/32/2331_2.png) [@riban](https://discourse.zynthian.org/u/riban)\
**Post date:** [November 24, 2024, 11:20pm UTC](https://discourse.zynthian.org/t/zynthian-dac-adac-light-ready-for-codec-development/10527/52 "2024-11-24T23:20:59Z")

</div>

The hardware is fine. We have a crystal creating the MCLK feeding PCM1808 which then creates the BCK & LRCK, feeding the PCM5102 and the RPi5. This works. I have audio input and output working on 8 channels. We are almost there. I just can’t get duplex. I can enable input or output. I need to better understand the dts.

---

<div class="post-metadata">

**Author:** ![le51](https://discourse.zynthian.org/user_avatar/discourse.zynthian.org/le51/32/1706_2.png) [@le51](https://discourse.zynthian.org/u/le51)\
**Post date:** [November 24, 2024, 11:25pm UTC](https://discourse.zynthian.org/t/zynthian-dac-adac-light-ready-for-codec-development/10527/53 "2024-11-24T23:25:11Z")

</div>

yes I agree. It totaly makes sense in a single stereo codec pow.  
With 4 of them, wich pcm1808 will generate the needed clocks to the PI ?

---

<div class="post-metadata">

**Author:** ![riban](https://discourse.zynthian.org/user_avatar/discourse.zynthian.org/riban/32/2331_2.png) [@riban](https://discourse.zynthian.org/u/riban)\
**Post date:** [November 24, 2024, 11:26pm UTC](https://discourse.zynthian.org/t/zynthian-dac-adac-light-ready-for-codec-development/10527/54 "2024-11-24T23:26:10Z")

</div>

We would choose one pcm1808 to create the clocks.

---

<div class="post-metadata">

**Author:** ![le51](https://discourse.zynthian.org/user_avatar/discourse.zynthian.org/le51/32/1706_2.png) [@le51](https://discourse.zynthian.org/u/le51)\
**Post date:** [November 24, 2024, 11:28pm UTC](https://discourse.zynthian.org/t/zynthian-dac-adac-light-ready-for-codec-development/10527/55 "2024-11-24T23:28:05Z")

</div>

yes, so other must be slave then ?

---

<div class="post-metadata">

**Author:** ![riban](https://discourse.zynthian.org/user_avatar/discourse.zynthian.org/riban/32/2331_2.png) [@riban](https://discourse.zynthian.org/u/riban)\
**Post date:** [November 24, 2024, 11:31pm UTC](https://discourse.zynthian.org/t/zynthian-dac-adac-light-ready-for-codec-development/10527/56 "2024-11-24T23:31:11Z")

</div>

Yes! We have one clock producer which is one of the PCM1808 and everything else is a clock consumer.

---

<div class="post-metadata">

**Author:** ![stojos](https://discourse.zynthian.org/user_avatar/discourse.zynthian.org/stojos/32/10833_2.png) [@stojos](https://discourse.zynthian.org/u/stojos)\
**Post date:** [November 24, 2024, 11:57pm UTC](https://discourse.zynthian.org/t/zynthian-dac-adac-light-ready-for-codec-development/10527/57 "2024-11-24T23:57:07Z")

</div>

Hm, it is strange that ALSA recognise both devices. Both `aplay -l` and `arecord -l` show device.

```auto
(venv) root@zynthian:~# arecord -l
****List of CAPTURE Hardware Devices****
card 0: zyndacadclite [zyndacadc-lite], device 1: 1f000a4000.i2s-dir-hifi dir-hifi-1 [1f000a4000.i2s-dir-hifi dir-hifi-1]
Subdevices: 1/1
Subdevice #0: subdevice #0
(venv) root@zynthian:~# aplay -l
****List of PLAYBACK Hardware Devices****
card 0: zyndacadclite [zyndacadc-lite], device 0: 1f000a4000.i2s-dit-hifi dit-hifi-0 [1f000a4000.i2s-dit-hifi dit-hifi-0]
Subdevices: 0/1
Subdevice #0: subdevice #0
(venv) root@zynthian:~#

```

I can’t get them working on zyntian. I can play on zynthian and I can see the two audio ins but audio in is not working .

I have used the following to set jack in zynthian

Jackd Options  
`-P 70 -s -S -d alsa -d hw:zyndacadclite -r 48000 -p 128 -n 2 -i 2 -o 2 -X raw`

I have added  
`capture_link:`  
and  
`playback_link:`  
in front of  
`simple-audio-card,dai-link@0 {`  
and  
`simple-audio-card,dai-link@1 {`  
so the fragment 3 looks like this:

```auto
        fragment@3 {
                // Configure and enable soundcard driver
                target = <&sound>;
                __overlay__ {
                        compatible = "simple-audio-card";
                        simple-audio-card,name = "zyndacadc-lite";
                        status = "okay";
                        capture_link: simple-audio-card,dai-link@0 {
                                format = "i2s";
                                bitclock-master = <&in_codec>;
                                frame-master = <&in_codec>;
                                cpu {
                                        sound-dai = <&i2s_clk_consumer>;
                                        dai-tdm-slot-num = <2>;
                                        dai-tdm-slot-width = <32>;
                                };
                                in_codec: codec {
                                        sound-dai = <&codec_in>;
                                };
                        };
                        playback_link: simple-audio-card,dai-link@1 {
                                format = "i2s";
                                bitclock-master = <&out_codec>;
                                frame-master = <&out_codec>;
                                cpu {
                                        sound-dai = <&i2s_clk_consumer>;
                                        dai-tdm-slot-num = <2>;
                                        dai-tdm-slot-width = <32>;
                                };
                                out_codec: codec {
                                        sound-dai = <&codec_out>;
                                };
                        };
                };
        };

```

---

<div class="post-metadata">

**Author:** ![Kirtai](https://discourse.zynthian.org/user_avatar/discourse.zynthian.org/kirtai/32/12530_2.png) [@Kirtai](https://discourse.zynthian.org/u/Kirtai)\
**Post date:** [November 25, 2024, 12:48am UTC](https://discourse.zynthian.org/t/zynthian-dac-adac-light-ready-for-codec-development/10527/58 "2024-11-25T00:48:09Z")

</div>

It’s just a pity this only works on a Pi5. I would love to use an older Pi as a multitrack recorder or mixer.

---

<div class="post-metadata">

**Author:** ![riban](https://discourse.zynthian.org/user_avatar/discourse.zynthian.org/riban/32/2331_2.png) [@riban](https://discourse.zynthian.org/u/riban)\
**Post date:** [November 25, 2024, 12:53am UTC](https://discourse.zynthian.org/t/zynthian-dac-adac-light-ready-for-codec-development/10527/59 "2024-11-25T00:53:17Z")

</div>

Earlier versions of RPi only had a single I2S interface. The RP1 chip that was added to the RPi5 to implement its i/o has several I2S interfaces. We can enable 4 of them in each direction giving us 8 inputs and 8 outputs.

You can get an external USB interface like the Tascam US-16x08 which is a really good option with compressors and 4-band eq in DSP on each of its 16 inputs.

---

<div class="post-metadata">

**Author:** ![riban](https://discourse.zynthian.org/user_avatar/discourse.zynthian.org/riban/32/2331_2.png) [@riban](https://discourse.zynthian.org/u/riban)\
**Post date:** [November 25, 2024, 11:37am UTC](https://discourse.zynthian.org/t/zynthian-dac-adac-light-ready-for-codec-development/10527/60 "2024-11-25T11:37:00Z")

</div>

I did some tests today, accessing the soundcard at the ALSA level.

If you access the cards with their device id then they can each be accessed, e.g. `hw:zyndacadclite,DEV=1`. Recording is resulting in hash so something is not right on that part of my card.

This doesn’t really help us as zynthian depends on jack which can only access one device as its main audio interface.

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