Dtoverlay midi-uart0 on pi5

Hello from Germany.

I already asked Brian, and he told me, that you are working on it…

Maybe you might give me a hint.

I am trying to establish a MiDi-Input an a Pi5. It seems that dtoverlay midi-uart0 doesnt work anymore. It should teak the UART clock for ttymidi to run the native MIDI-Bad rate. However, ttymidi -b 38400 -v outputs garbage when pressng the keyboard.

Doi you have an idea?

Thiis is my /boot/firmware/config.txt so far:

# For more options and information see
# http://rptl.io/configtxt
# Some settings may impact device functionality. See link above for details

# Uncomment some or all of these to enable the optional hardware interfaces



# Automatically load initramfs files, if found
auto_initramfs=1

# Enable DRM VC4 V3D driver
dtoverlay=vc4-kms-v3d,noaudio
max_framebuffers=2

# HIFIBerry
dtoverlay=hifiberry-dacplus
force_eeprom_read=0


# Don't have the firmware create an initial video= setting in cmdline.txt.
# Use the kernel's default instead.
disable_fw_kms_setup=1

# Run in 64-bit mode
arm_64bit=1

# Disable compensation for displays with overscan
disable_overscan=1
# Disable Bluetooth
dtoverlay=disable-bt
# Run as fast as firmware / board allows
arm_boost=1

# Enable Status-LEDs
#dtoverlay=gpio-led,gpio=23,label=cpuload,trigger=cpu
dtoverlay=gpio-led,gpio=23,label=wifi,trigger=rfkill0
dtoverlay=gpio-led,gpio=24,label=heartbeat,trigger=heartbeat
dtoverlay=gpio-led,gpio=25,label=mmc,trigger=mmc0


[cm4]
# Enable host mode on the 2711 built-in XHCI USB controller.
# This line should be removed if the legacy DWC2 controller is required
# (e.g. for USB device mode) or if USB support is not required.
otg_mode=1

[all]
# Enable UART for classic MIDI and disable BT

dtoverlay=disable-bt

#GPIO15
dtparam=uart0_console=on
        

dtparam=uart0=on
dtoverlay=midi-uart0

# Daten auf /dev/serial0


Best regards.
Thorsten

Hi @Stupps !

I was doing some research and found this:

https://forums.raspberrypi.com/viewtopic.php?t=361321

It point me to make some tests:

# cat /sys/kernel/debug/clk/clk_summary
                                 enable  prepare  protect                                duty  hardware
   clock                          count    count    count        rate   accuracy phase  cycle    enable
-------------------------------------------------------------------------------------------------------
 rv3028-clkout                        0        0        0       32768          0     0  50000         Y
 clk-hifiberry-dacpro                 1        1        0    22579200          0     0  50000         Y
 fw-clk-vec                           0        0        0           0          0     0  50000         Y
 fw-clk-pixel-bvb                     0        0        0    75000000          0     0  50000         Y
 fw-clk-m2mc                          0        0        0   120000000          0     0  50000         Y
 fw-clk-hevc                          0        0        0   250000000          0     0  50000         Y
 fw-clk-pixel                         0        0        0           0          0     0  50000         Y
 fw-clk-isp                           0        0        0   250000000          0     0  50000         Y
 fw-clk-v3d                           0        0        0   250000000          0     0  50000         Y
 fw-clk-core                          0        0        0   500000000          0     0  50000         Y
 fw-clk-arm                           0        0        0  2000000000          0     0  50000         Y
 108MHz-clock                         0        0        0   108000000          0     0  50000         Y
 27MHz-clock                          0        0        0    27000000          0     0  50000         Y
 otg                                  1        1        0   480000000          0     0  50000         Y
 osc                                  4        4        1    54000000          0     0  50000         Y
    tsens                             0        0        0     3375000          0     0  50000         Y
    otp                               0        0        0    13500000          0     0  50000         Y
    timer                             0        0        0     1000000          0     0  50000         Y
    plld                              5        5        0  3000000091          0     0  50000         Y
       plld_dsi1                      1        1        0   750000023          0     0  50000         Y
       plld_dsi0                      1        1        0    11718751          0     0  50000         Y
       plld_per                       2        2        0   750000023          0     0  50000         Y
          emmc2                       1        1        0   100000003          0     0  50000         Y
          dsi1e                       0        0        0   100000003          0     0  50000         Y
          emmc                        0        0        0   250000007          0     0  50000         Y
          uart                        0        0        0    48000001          0     0  50000         Y
       plld_core                      1        1        0   600000019          0     0  50000         Y
    pllc                              5        5        0  2592000000          0     0  50000         Y
       pllc_per                       1        1        0   648000000          0     0  50000         Y
       pllc_core2                     1        1        0    10125000          0     0  50000         Y
       pllc_core1                     1        1        0    10125000          0     0  50000         Y
       pllc_core0                     1        1        0    10125000          0     0  50000         Y
    pllb                              2        2        0  3999999984          0     0  50000         Y
       pllb_arm                       1        1        0  1999999992          0     0  50000         Y
    plla                              4        4        1  2999999988          0     0  50000         Y
       plla_ccp2                      1        1        0    11718750          0     0  50000         Y
       plla_dsi0                      1        1        0    11718750          0     0  50000         Y
       plla_core                      2        2        1   499999998          0     0  50000         Y
          h264                        0        0        0   499999998          0     0  50000         Y
          isp                         0        0        0   499999998          0     0  50000         Y
          vpu                         5        5        1   500000000          0     0  50000         Y
             fe804000.i2c_div         1        1        1      100000          0     0  50000         Y
             aux_spi2                 0        0        0   500000000          0     0  50000         N
             aux_spi1                 0        0        0   500000000          0     0  50000         N
             aux_uart                 1        1        0   500000000          0     0  50000         Y
             peri_image               0        0        0   500000000          0     0  50000         Y
 uart0_pclk                           1        1        0    58982400          0     0  50000         Y
 dsi1p                                0        0        0           0          0     0  50000         Y
 dsi0p                                0        0        0           0          0     0  50000         Y
 dsi0e                                0        0        0           0          0     0  50000         Y
 cam1                                 0        0        0           0          0     0  50000         Y
 cam0                                 0        0        0           0          0     0  50000         Y
 dpi                                  0        0        0           0          0     0  50000         Y
 tec                                  0        0        0           0          0     0  50000         Y
 smi                                  0        0        0           0          0     0  50000         Y
 slim                                 0        0        0           0          0     0  50000         Y
 gp2                                  0        0        0           0          0     0  50000         Y
 gp1                                  0        0        0           0          0     0  50000         Y
 gp0                                  0        0        0           0          0     0  50000         Y
 dft                                  0        0        0           0          0     0  50000         Y
 aveo                                 0        0        0           0          0     0  50000         Y
 pcm                                  0        0        0           0          0     0  50000         Y
 pwm                                  0        0        0           0          0     0  50000         Y
 sdram                                0        0        0           0          0     0  50000         Y
 hsm                                  0        0        0           0          0     0  50000         Y
# ls /sys/kernel/debug/clk
108MHz-clock  aux_uart	clk_dump	      clk_summary  dsi0p  emmc2		    fw-clk-hevc   fw-clk-pixel-bvb  gp1   isp  pcm	   plla_core  pllc	  pllc_per   plld_dsi1	    sdram  timer       vpu
27MHz-clock   aveo	clk-hifiberry-dacpro  dft	   dsi1e  fe804000.i2c_div  fw-clk-isp	  fw-clk-v3d	    gp2   osc  peri_image  plla_dsi0  pllc_core0  plld	     plld_per	    slim   tsens
aux_spi1      cam0	clk_orphan_dump       dpi	   dsi1p  fw-clk-arm	    fw-clk-m2mc   fw-clk-vec	    h264  otg  plla	   pllb       pllc_core1  plld_core  pwm	    smi    uart
aux_spi2      cam1	clk_orphan_summary    dsi0e	   emmc   fw-clk-core	    fw-clk-pixel  gp0		    hsm   otp  plla_ccp2   pllb_arm   pllc_core2  plld_dsi0  rv3028-clkout  tec    uart0_pclk

# ls /sys/kernel/debug/clk/uart0_pclk
clk_accuracy  clk_duty_cycle  clk_enable_count	clk_flags  clk_max_rate  clk_min_rate  clk_notifier_count  clk_phase  clk_prepare_count  clk_protect_count  clk_rate

# cat /sys/kernel/debug/clk/uart0_pclk/clk_rate
58982400

# echo "28982400" > /sys/kernel/debug/clk/uart0_pclk/clk_rate
-bash: echo: write error: Permission denied

As you see, i didn’t find an easy way of changing UART clock yet. Perhaps you have better luck. If not, i hope some smart guy from the RPI foundation will help with this.

Indeed, they should bring us something like the midi-uart0 overlay :wink:

The best,

BTW, i’m opening this thread. More brains on this could help too :wink:

1 Like

Ahhh! I see you opened a thread in the RPI forums:

https://forums.raspberrypi.com/viewtopic.php?t=365126

Those wanting to help, please, put some pressure on the RPI foundation by posting to the above thread :wink:

regards,

1 Like

Hello and sincere thankyou to you.
Well, it’s good to know that there IS an issue about midi-uart0. I was wondering and trying for about two weeks now.
BTW: Envoking the dtoverlay midi-uart0 more than one time leads to the errormessage which I described in the raspberry-forum. This however seems NOT to be the problem.
To me it seems that simply spoken dtoverlay midi-uart0 doesn’t work at all at Pi5.

And another thing which Brian dipped my nose at:
There are multiple sourcecode of ttymidi.c.
The latest ones accepts -b 31250 as the Baudrate-parameter. The earlier ones did not.
Just to have in mind.

Best regards.
Thorsten

Obviously!! The Pi5 has a very different I/O subsystem, managed by a new chip, the RP1.

I will take a look. Anyway, 31250 is not a standard baud rate and can’t be set from the standard Linux OS side. You can request it, but you are not going to get it in a “normal” system. It must be supported by the kernel driver, what is not the case in standard systems.

Or as we did in the past, we could simply tweak the base UART clock to fake the system, and then request a standard baud rate that gives a close-enough result.

Regards,

1 Like

Hi @Pi5 lovers!

The MIDI uart is fixed in bookworm 's latest firmware update. Take a look to the conversation:

https://forums.raspberrypi.com/viewtopic.php?p=2215536#p2215536

It should be fixed by updating your zynthian software. If not, try:

rpi-update

Cheers!

5 Likes

Just in order to revive this topic a bit, @jofemodo and @riban:

Is there still in place a general development timeline, for RPi5 support in Oram 64 and - consequentially - the release of the V5+Pi5 upgrade kit (or possibly even a refashioned aluminum case)?

I seem to gather from the forum that switching to RPi5 appears to be posing more arduous technical challenges than foreseen.

1 Like