Hi, announcment if the RP5 triggered an instant V5 order. 
Thermal block will not fit i assume. But as i understand drill holes and gpio header are the same.
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they have swapped Ethernet and USB ports.
The MIPI/DSI connector has changed of location too.
And for having the benefit of the PCIe lane, additional hardware is needed.
so 
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Ha! Again?
iron saw requierd?
Well, as you can see, they swapped the USB & ethernet ports AGAIN. This complicates the our life, here in Zynthian Labs. We have to modify the V5 alucase and also the main board. We really didnāt think they will be swapping back this connectors again, so the Main Board profile donāt match the new RPi5 connectors layout.
To adapt it, you need some surgery and rewiring the USB-B connector . Not difficult, but annoying.
Regarding the alucase, some surgery will be required too, and of course, the thermal block must be completely redesigned.
We are thinking of releasing an āupdate kitā when ready, so initial V5 owners could update to RPi5. The price for the update kit would be as low as possible. We donāt like to take profit from this, but having happy V5 owners!
All the best,
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I think new MIPI/DSI connector location is problematic too.
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The rear DSI connector is in the same place, but the pin density has doubled, so we would need a special cable, but the RPi foundation seem to have thought about ti and they will offer this cable, so little problem here.
The connector swapping is the fucking issue here. And i can imagine a good reason for it, but we have to work with it.
Regards
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That is exactly what I hoped the ZynthianLabs would do for V5 1.0 owners, in the most authentic Zynthianic spirit, straight away when I got the news of the Pi5! 
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so far I understand, this connector (the one close to the wireless chip) is now used for the PCIe add on Hat while the 2 MIPI (CSI and/or DSI) are now close one to the another at the place where the audio jack was:
and yes, these MIPI connectors are advertised as 4 lanes peripherals, so they should not directly be compatible with the actual v5 MIPI/DSI display without some low level tweaking. But I think (hope) the RBPi foundation will do this dirty job.
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What we use in V5 is the DSI connector that is placed aside the WIFI chip. Itās supposed to be compatible, but with smaller pitch (0.5mm instead of 1mm).
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Nice having that āUARTā connector between the āmini-HDMIā ports. Anybody know what connector type that is?
yes indeed. + RTC + button + Fan control + a big step in perfs all of this is nice.
But no native M2-M conector for a NVMe drive, itās sooo disappointing 
But what I found really interesting, is the new RP1 chip (from RBPi foundationās post):
RP1 is our I/O controller for Raspberry Pi 5, designed by the same team at Raspberry Pi that delivered the RP2040 microcontroller, and implemented, like RP2040, on TSMCās mature 40LP process. It provides two USB 3.0 and two USB 2.0 interfaces; a Gigabit Ethernet controller; two four-lane MIPI transceivers for camera and display; analogue video output; 3.3V general-purpose I/O (GPIO); and the usual collection of GPIO-multiplexed low-speed interfaces (UART, SPI, I2C, I2S, and PWM). A four-lane PCI Express 2.0 interface provides a 16Gb/s link back to BCM2712.
They are on it since 2016 and have spent $15 million. This will be for sure a central part of their future production.
This piece of hardware drives now all the GPIO stuff, and if is like the RP2040 with its PIO system. So maybe it could be possible to assign more pins to I2S data lines and have multichannel audio in/out 
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Iām not 100% sure bit I think itās a Qwiic JST connector. This would make sense because they are already in use on the Raspberry Pi Debug Probe (for the Raspberry Pi Pico but also has a standard UART connection) and the Raspberry Pi Pico H uses it for the debug connection (instead of the unpopulated pin header)
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Thank you @VoidField101 - I see that they are readily available, Iāll try it when I get the pi5 and post here with the results.